1. Field of the Invention
The present invention relates to a semiconductor memory device, and in particular to a semiconductor memory device in which word lines are hierarchized into main word lines and sub-word lines, and data lines are hierarchized into local data lines and global data lines. More particularly, the invention relates to a dynamic random access memory having a hierarchical word line structure and a hierarchical data input/output line structure. More specifically, the invention relates to an arrangement of hierarchical data lines in the dynamic random access memory having the hierarchical word line structure and the hierarchical data line structure.
2. Description of the Background Art
FIG. 8 schematically shows a structure of a memory cell array in a semiconductor memory device in the prior art. In FIG. 8, the memory array in this semiconductor memory device is divided into a plurality of memory blocks MB00-MBnm each having a plurality of memory cells MC arranged in rows and columns. The memory blocks aligned in the column direction form column blocks CB#0-CB#n respectively, and the memory blocks aligned in the row direction form row blocks RB#0-RB#n, respectively. For example, memory blocks MB00, MB10, . . . , MBn0 form a column block CB#0, and memory blocks MB00, MB01, . . . , MB0m form a row block RB#0.
A word line WL is arranged commonly for the memory blocks included in a row block. A column select line CSL is arranged commonly for the memory blocks included in a column block. A row decoder RD transmits a word line select signal onto word lines WL, and a column decoder CD transmits a column select signal onto column select lines CSL.
For each of memory blocks MB00-MBnm, there are arranged local data I/O buses LIO00-LIOnm extending in the row direction, respectively. These local data I/O buses LIO00-LIOnm are arranged along the row direction only within regions at which corresponding memory blocks MB00-MBnm are arranged, respectively. Global data I/O buses GIO0-GIOm are arranged in the column direction for column blocks CB#0-CB#m, respectively. Global data I/O buses GIO0-GIOm are provided for the memory blocks included in the corresponding column blocks CB#0 to CB#m, respectively. For example, global data I/O bus GIO0 is commonly provided for memory blocks MB00, MB10, . . . , MBn0 included in column block CB#0.
Local data I/O buses LIOji are selectively connected to global data I/O bus GIOj by a not shown row block select gate which is turned on in response to a row block select signal. The local data I/O bus, which is provided for the memory block included in the selected row block, is connected to the corresponding global data I/O bus.
By providing a hierarchical structure of the data I/O buses formed of local data I/O buses LIO and global data I/O buses, input and output of multi-bit data can be performed easily. Further, by arranging the global data I/O buses at regions (word line shunt regions) between the memory blocks, it is possible to suppress increase of an area occupied by the global data I/O buses, and therefore input and output of multi-bit data can be performed easily without increasing an area occupied by the array. The memory array has a row block driven to the selected state at a time, and the nonselected row blocks can be kept at a precharged state, whereby a current consumption can be reduced.
The global data I/O buses GIO0-GIOm and local data I/O buses LIO00-LIOnm have bus widths appropriately determined, respectively.
FIG. 9 shows a structure of memory cell MC shown in FIG. 8. In FIG. 9, memory cell MC has a capacitor MQ for storing information, and an access transistor MT formed of an n-channel MOS transistor which is turned on in response to a signal potential on word line WL and thereby connects capacitor MQ to a bit line BL. Another memory cell is arranged at a crossing between a complemental bit line /BL and another word line (not shown). This structure is called a "folded bit line" structure. Memory capacitor MQ receives on one electrode node a constant reference voltage VCP which is usually half the power supply voltage, and stores, on the other electrode node (i.e., storage node), electric charges which are positive or negative with reference to voltage VCP. When reading data, a potential on bit line BL, which changes in accordance with data stored in memory cell MC, is differentially amplified with the reference voltage at a precharge voltage on complemental bit line /BL.
Memory cell MC shown in FIG. 9 stores information in capacitor MQ in an electric charge form. When the charges are reduced due to a leak current to a substrate or bit line BL, the stored information would be lost. In order to prevent the loss of stored information, restoring of data is periodically performed at predetermined intervals. This restoring is call refreshing. During this refreshing, external devices cannot access this semiconductor memory device. Further, charging and discharging of the bit lines BL and /BL are performed during the refreshing. Therefore, in order to reduce the current consumption and suppress reduction in access efficiency, the refresh period is set as long as possible.
A larger storage capacity of the semiconductor memory device requires a larger array area. For example, a memory device of 256 Mbits has a storage capacity four times larger than that of a memory device of 64 Mbits. According to simple calculation, therefore, memory cells in the memory device of 256 Mbits must be double in number in both the row and column directions, so that memory cells connected to each word line WL increase in number, and lengths of interconnections of word lines also increase. The increase in length of word lines WL and the increase in number of the memory cells result in increase in interconnection resistance and interconnection capacitance of word lines WL, so that word lines WL cannot be driven rapidly to the selected state, and therefore the access time increases.
For fast driving of the word lines in the semiconductor memory device of a large capacity, such a manner may be employed that the word lines are divided into main word lines and sub-word lines actually connected to memory cells for allowing fast transmission of a word line select signal to an end of the main word line.
FIG. 10 schematically shows a structure of an array in a semiconductor memory device having such a hierarchical word line structure formed of main word lines and sub-word lines. FIG. 10 shows memory blocks MBia-MBkb included in two column blocks in three row blocks RB#i, RB#j and RB#k. Memory blocks MBia, MBja and MBka are included in column block CB#a, and memory blocks MBib, MBjb and MBkb are included in column block CB#b. Row block RB#i includes memory blocks MBia and MBib. Row block RB#j includes memory blocks MBja and MBjb. Row block RB#k includes memory blocks MBka and MBkb.
In each of memory blocks MBia-MBkb, a sub-word line SWL is arranged for each row of the memory cells. The memory cells in the corresponding rows are connected to these sub-word lines SWL, respectively. In each row block, a main word line MWL is arranged commonly to the memory blocks included in the same row block. The main word line MWL is arranged commonly to sub-word lines SWL arranged for the corresponding row in the corresponding row block. Therefore, main word line MWL extends entirely over the corresponding row block, and the sub-word line SWL extends in the row direction only within the corresponding memory block.
A sense amplifier band SA#a including sense amplifiers, which will be described later, is arranged in a region extending in the row direction between row blocks RB#i and RB#j. A sense amplifier band SA#b including sense amplifiers is arranged in a region extending in the row direction between row blocks RB#j and RB#k. The sense amplifiers in sense amplifier bands SA#a and SA#b have a so-called shared sense amplifier structure, and are operable to sense and amplify memory cell data in the corresponding columns in the adjacent memory blocks. Sense amplifier bands SA#a and SA#b are provided with local data I/O buses, which extend in the row direction within the corresponding memory block regions, respectively, but are not shown in FIG. 10 for simplifying the figure.
In the sense amplifier band SA#a, there is further arranged a sub-decode signal line SDA which extends in the row direction for transmitting a sub-decode signal from row decoder RD. Likewise, a sub-decode signal line SDB is arranged in the sense amplifier band SA#b for transmitting a sub-decode signal from row decoder RD. As will be described later in detail, main word line MWL simultaneously sets a plurality of (e.g., four) sub-word lines in one memory block to the selected or designated state, and one of the sub-word lines designated by the main word line is selected in accordance with the sub-decode signals on sub-decode signal lines SDA and SDB.
Sub-decoders for driving the sub-word lines to the selected state in accordance with the signal potential on the main word line MWL and the sub-decode signal are arranged in a sub-decode band SD#a, which extends in the column direction through a region between column blocks CB#a and CB#b. Likewise, sub-decoders which drive the sub-word lines to the selected state in accordance with the signal potential on the main word line and sub-decode signal SDA are arranged in a sub-decode band SD#b between column block CB#b and adjacent column block (not shown).
Sub-decode signal line SDB transmits a sub-decode signal through local sub-decode signal lines SDBa and SDBb, which are arranged along the column direction for memory blocks MBja and MBka, in sub-decode band SD#a, respectively. Sub-decode signal line SDA transmits a sub-decode signal to memory blocks MBib and MBjb through local sub-decode signal lines SDAa and SDAb, which extends only along memory blocks MBib and MBjb in the column direction, respectively.
Local sub-decoded signal lines for sub-decode signal lines SDA and SDB are arranged extending in the column direction and are arranged alternately in the sub-decode bands SD#a and SD#b, respectively. Thereby, one memory block (e.g., MB#jb) is driven such that the sub-word lines at the opposite sides thereof are driven by the sub-decoders included in the sub-decode bands SD#a and SD#b. Therefore, the sub-decoder included in the sub-decode band SD#a is commonly used by two memory blocks neighboring to each other in the row direction, and the sub-decoder included in the sub-decode band SD#b is commonly used by two memory blocks neighboring to each other in the row direction. By utilizing the sub-decode signals in such a manner, it is possible to increase an allowable pitch of decode circuits included in row decoder RD. Also, by utilizing the sub-decode signals and alternately arranging the local sub-decode signal lines in the sub-decode bands, it is possible to increase an allowable pitch of sub-decoders decoding the sub-decode signals.
FIG. 11 schematically shows a structure of a portion related to one main word line MWL in one memory block MB. In FIG. 11, four sub-word lines SWL0-SWL3 are arranged for main word line MWL in memory block MB. Memory cells MC are arranged at crossings between sub-word lines SWL0-SWL3 and bit line pair BLP.
Sub-decoders SBD0-SBD3 are arranged for sub-word lines SWL0-SWL3, respectively. Sub-decoder SBD0 drives sub-word line SWL0 to the selected or nonselected state in accordance with the signal potential on main word line MWL and sub-decode signal SD0 from sub-decode signal line SDA. Sub-decoder SBD1 drives corresponding sub-word line SWL1 to the selected state in accordance with the signal potential on main word line MWL and sub-decode signal SD1 on sub-decode signal line SDB. Sub-decoder SBD2 drives sub-word line SWL2 to the selected state in accordance with the signal potential on main word line MWL and sub-decode signal SD2 from sub-decode signal line SDA. Sub-decoder SBD3 drives sub-word line SWL3 to the selected state in accordance with the signal potential on main word line MWL and sub-decode signal SD3 from sub-decode signal line SDB. Sub-decoders SBD0 and SBD2 are arranged at one side of the memory block MB, and sub-decoders SBD1 and SBD3 are arranged at the other side of the memory block MB. Thus, a so-called "alternated sub-decoder arrangement" is employed. Thereby, a pitch of the sub-decoders in the column directions is equal to two pitches of the sub-word lines, so that the sub-decoders can be arranged without a difficulty. Sub-decode signals SD0-SD3 are obtained by decoding, e.g., least significant 2 bits of row address signal, and are adapted to specify one of four sub-word lines SWL0-SWL4.
By using the hierarchical word line structure shown in FIG. 11, the word line can be rapidly driven to the selected state as shown in FIG. 12.
FIG. 12 schematically shows a structural relationship between main word line MWL and sub-word lines SWLj0-SWLjn in row block RB#j. The signal potential on main word line MWL is transferred to sub-decoders SBD#0-SBD#p. Sub-decoder SBD#0 drives sub-word lines SWLj0 and SWLh, and sub-decoder SBD#1 drives sub-word lines SWLj2 and SWLj3. Sub-decoder SBD#p drives sub-word lines SWLj(n-1) and SWLjn.
Sub-decoders SBD#0-SBD#p are arranged in the sub-decode band as shown in FIG. 10. Sub-decode bands SD#a and SD#b are regions between the memory blocks corresponding to so-called word line shunt regions, i.e., regions where no memory cell is present. Sub-decoders SBD#0-SBD#b are arranged at the word line shunt regions, respectively. Main word line MWL and sub-decode signal lines SDA and SDB are not connected to the memory cell, and therefore can transmit signals at a high speed. Therefore, arrangement of sub-decoders SBD#0-SBD#p at the word line shunt regions allows fast driving of sub-word lines SWLJ0-SWLjn connected to the memory cells to the selected state, so that the row select operation can be performed by driving the word lines to the selected state at a high speed even if the storage capacity is large.
FIG. 13 shows more specifically the structures of sub-decode bands SD#a and SD#b and sense amplifier bands SA#a and SA#b for memory block MB#jb shown in FIG. 10. FIG. 13 representatively shows sub-decoders SBD2 and SBD3 for two sub-word lines SWL2 and SWL3 included in memory block MB#jb, respectively.
In memory block MB#jb, there are representatively shown four bit line pairs BLPa, BLPb, BLPc and BLPd which are simultaneously selected by one column select signal.
At sense amplifier band SA#a, there are arranged a sense amplifier SAb for differentially amplifying and latching the potentials on bit line pair BLPa and a sense amplifier SAd for differentially amplifying and latching the potentials on bit line pair BLPd. Data sensed and amplified by sense amplifiers SAb and SAd are transmitted onto local data I/O buses LIOB and LIOd extending in the column direction through column select gates (not shown), respectively.
Signals on bit line pairs BLPa and BLPc are differentially amplified and latched by sense amplifiers SAa and SAc arranged at sense amplifier band SA#b, respectively. Data sensed and amplified by sense amplifiers SAa and SAc are transmitted through local data I/O buses LIOa and LIOc arranged in sense amplifier band SA#b for memory block MBjb (column select gate is not shown). Each of these local data I/O buses LIOa-LIOd is formed of a first level aluminum interconnection layer.
At sub-decode band SD#a, there are arranged decode signal lines SD0, SD2, ZSD0 and ZSD2 extending in the column direction for transmitting decode signals SD0 and SD2 as well as complementary decode signals ZSD0 and ZSD2 (here, signals and corresponding interconnection lines are indicated by the same reference characters). There are arranged global data I/O buses GIOa and GIOb extending in the column direction. Global data I/O bus GIOa is connected to local data I/O bus LIOa through a block select gate (not shown). Global data I/O bus GIOb is connected to local data I/O bus LIOb through the block select gate (not shown) at a portion located in the sense amplifier band SA#a.
Signal lines SD0, SD2, ZSD0 and ZSD2 as well as a ground line Ga and global data I/O buses GIOa and GIOb, which are arranged in the sub-decode band SD#a, are formed of second level aluminum interconnections higher than the first level aluminum interconnection layer.
Sub-decoder SBD2 is formed at a region between signal lines SD2 and ZSD2. Sub-decoder SBD2 includes a p-channel MOS transistor P1, which is turned on to transmit sub-decode signal SD2 onto sub-word line SWL2 when a signal on main word line MWL is at L-level indicative of the selected state, an n-channel MOS transistor N1 which is turned on to transmit ground voltage GND on ground line Ga to sub-word line SWL2 when sub-decode signal ZSD2 is at H-level indicative of the nonselected state, and an n-channel MOS transistor N2 which is turned on to transmit ground voltage GND on ground line Ga to sub-word line SWL2 when the signal potential on main word line MWL is at H-level indicative of the nonselected state.
Sub-decode signals ZSD0 and SD0 are transferred to sub-decoder SBD0 (not shown) neighboring in the column direction.
Global data I/O buses GIOa and GIOb are arranged adjacent to ground line Ga, and thereby the lengths of sub-decode lines SD0, SD2, ZSD0 and ZSD2 in the row direction are reduced. The reason for this is to increase sufficiently the allowable sizes, in the row direction, for transistors P1, N1 and N2 in the sub-decoder SBD2, and align the sub-decoders in the column direction.
In the sub-decode band SD#b, global data I/O buses GIOc and GIOd formed of the second level aluminum interconnection layer extend in the column direction. Global data I/O bus GIOc has a portion, which is located in sense amplifier band SA#b connected to local data I/O bus LIOc through a block select gate (not shown). Global data I/O buses GIOd has a portion, which is located in sense amplifier band SA#a, connected to local data I/O bus LIOd through a block select gate (not shown).
In sub-decode band SD#b, there are arranged signal lines which extend in the column direction for transmitting sub-decode signals SD1, SD3, ZSD1 and ZSD3, respectively. Signal lines SD1, SD3, ZSD1 and ZSD3 do not extend beyond memory block MB#jb. Sub-decoder SBD3 includes a p-channel MOS transistor P2 which transmits sub-decode signal SD3 from signal line SD3 to sub-word line SWL3 when the signal potential on main word line MWL is at L-level, an n-channel MOS transistor N3 which is turned on to transmit ground voltage GND on ground line Gb to sub-word line SWL3 when sub-decode signal ZSD3 is at H-level, and an n-channel MOS transistor N4 which is turned on to transmit ground voltage GND on ground line Gb to sub-word line SWL3 when the signal potential on main word line MWL is at H-level.
Ground line GND and signal lines SD1, SD3, ZSD1 and ZSD3 are formed of the second level aluminum interconnections, respectively. Ground lines Ga and Gb extend in the column direction and are provided commonly for the memory blocks in the column block for transmitting the ground voltage to the sub-decoders. In this sub-decode band SD#b, global data I/O buses GIOc and GIOd are arranged adjacent to the ground line Gb. The reason for this is to keep a sufficient large distance in the row direction between signal lines SD3 and ZSD3, and thereby increase sufficiently the allowable sizes, in the row direction, for transistors P2, N4 and N3 in the sub-decoder SBD3, and align the sub-decoders in the column direction.
Signal lines SD1 and ZSD1 are connected to sub-decoder SBD1 (not shown in FIG. 13). An operation of the structure shown in FIG. 13 will be described below with reference to FIG. 14. FIG. 14 representatively shows address signal bits A0 and A1. The rest of more significant address signal bits are applied in a similar manner. Reference characters "GIOi" and "ZGIOi" indicate global data I/O lines of the data I/O bus which are complementary with each other.
Before time t0, row address strobe signal /RAS is inactive at H-level, and global data I/O lines GIOi and ZGIOi have been precharged to H-level.
At time t0, row address strobe signal /RAS falls to L-level to start the memory cycle. Address bits (A1, A0) applied at this time are (1, 0), and sub-word line SWL2 is designated among sub-word lines SWL0-SWL3, so that sub-decode signal SD2 rises to H-level.
Concurrently, the potential on main word line MWL corresponding to the addressed row falls from H-level to L-level. In the sub-decoder SBD2, p-channel MOS transistor P1 is turned on, and sub-word line SWL2 is driven to H-level. In sub-decoder SBD2, both MOS transistors N1 and N2 are turned off.
In sub-decoder SBD3, signal SD3 set to L-level is transmitted onto sub-word line SW3 through p-channel MOS transistor P2, and sub-word line SWL3 maintains the nonselected state. At this time, signal ZSD3 is at H-level, and n-channel MOS transistor N3 is turned on to transmit ground potential GND on ground line Gb to nonselected sub-word line SWL3, so that this sub-word line SWL3 is kept at the nonselected state. When this word line selection is completed, sense amplifiers SAa-SAd are activated, and the potential difference appearing on each bit line pair is differentially amplified and latched.
At time t1, column address strobe signal /CAS falls, so that the column selection operation starts. At this time, address signal bits A1 and A0 are (0, 0), and for example, bit line pair BLPa is selected. In this state, sense amplifier SAa is selected and connected to local data I/O bus LIOa, and data on local data I/O bus LIOa is transmitted onto global data I/O bus GIOa. At time t1, a write instructing signal /WE is at L-level, and writing of data "0" is instructed. Therefore, data at L-level is transmitted from global data I/O bus GIOa through local data I/O bus LIOa, and data "0" is written into the selected memory cell. At this time, data at H-level is transmitted onto global data I/O line ZGIOi. The above operation occurs on each global data I/O bus.
When data writing is completed, column address strobe signal /CAS is temporarily raised to H-level, and thereby the column select operation is completed. Then, column address strobe signal ICAS is fallen to L-level again at time t2. In this state, write data DQ is "1" at H-level. Address signal bits A1 and A0 are 0 and 1, respectively, so that another bit line pair is selected. In this state, the potential on global data I/O line GIOi rises to H-level in accordance with the write data, and the potential on complementary global data I/O line ZGIOi falls to L-level. Then, a memory cell connected to the selected bit line pair are supplied with write data on bit line pair BLP through local data I/O bus LIO. In the structure shown in FIG. 13, four columns are simultaneously selected, and data of 4 bits are written. However, FIG. 14 shows a waveform of data of only one bit.
When writing of memory cell data is completed, column address strobe signal /CAS is raised to H-level again. Upon elapsing of a predetermined period (i.e., CAS precharge period), column address strobe signal /CAS is lowered to L-level again at time t3. In this state, column address signal bits A1 and A0 are 1 and 0, respectively, and still another bit line pair is selected. Write data DQ is 0, so that data of "0" is written onto the selected bit line pair BLP through corresponding global data I/O bus GIO, corresponding local data I/O bus LIO and corresponding sense amplifier SA. Therefore, global data I/O bus line GIOi maintains L-level, and complementary global data I/O bus line ZGIOi maintains H-level. When this data writing is completed, column address strobe signal /CAS is raised to H-level, and the column select operation is completed.
At time t4, column address strobe signal /CAS is lowered to L-level. Address signal bits A1 and A0 at this time are 1 and 1, respectively, and yet another bit line pair is selected. Write data DQ is "1". Therefore, data of "1" is written onto the selected bit line pair BLP through corresponding global data I/O bus GIO, corresponding local data I/O bus LIO and corresponding sense amplifier SA. In this state, global data I/O bus lines GIOi and ZGIOi are supplied with data at H-level and L-level, respectively.
At time t5, row address strobe signal /RAS is raised to H-level, and the data write operation is completed. Thereby, the sub-row decoder is reset, so that sub-decode signal SD2 falls to L-level, and the sub-word line SWL2 attains the nonselected state of L-level.
The foregoing mode in which data writing is performed by toggling column address strobe signal /CAS with row address strobe signal /RAS held at L-level is known as a page write mode, which is employed for fast writing of data.
In the above data write operation, the potentials on bus lines GIOi and ZGIOi of each global data I/O bus fully swing between the power supply voltage and the ground voltage, so that the following problem arises.
FIG. 15 schematically shows an interconnection layout at the sub-decode band. In FIG. 15, the same interconnection layer (second level aluminum interconnection layer) provides a sub-decode signal line 900 transmitting sub-decode signal SDi, a global data I/O line 902 performing data input/output, a complementary global data I/O line 904, a ground line 906 transmitting ground voltage GND and sub-decode signal line 908 transmitting sub-decode signal ZSDi which are spaced from each other. A parasitic capacitance 910 is formed between global data I/O line 904 and ground line 906 formed of the same interconnection layer. Global data I/O line 904 receives a signal, which fully swings between the power supply voltage and the ground voltage, in the write operation.
FIG. 16 schematically shows a structure of a portion related to one nonselected memory cell. Memory cell MC is arranged between nonselected sub-word line SWL and bit line BL. Nonselected sub-word line SWL is connected to ground line 906 through a sub-decode circuit. Global data I/O line 904 neighbors to ground line 906. Memory cell MC includes capacitor MQ, and access transistor MT for connecting capacitor MQ to bit line BL in response to the signal potential on sub-word line SWL.
In the page mode operation, sense amplifier SA is active while row address strobe signal /RAS is active, and differentially amplifies and latches the potentials on bit lines BL and /BL. Therefore, the potentials on bit lines BL and /BL are held at levels of power supply voltage VCC and ground voltage GND. The operation will be discussed in connection with the state that the potential on bit line BL is held at the ground voltage level, i.e., L-level, and the potential on the complementary bit line /BL is held at the power supply voltage level, i.e., H-level in accordance with data of the memory cell connected to the selected sub-word line (not shown). It is assumed that memory cell MC has stored data at H-level.
Sub-word line SWL is nonselected, and therefore is fixed at the ground voltage level. When this sub-word line SWL attains the ground voltage level, the access transistor MT is turned off to isolate memory cell capacitor MQ from bit line BL. However, when the page mode access is performed as shown in FIG. 14, a write pulse of a predetermined time width is generated in accordance with activation of column address strobe signal /CAS, and the potential on global data bus I/O line 904 changes between the power supply voltage and ground voltage GND. After completion of writing, the potential on global data I/O line is precharged to the power supply voltage level.
Therefore, when data at L-level is transmitted onto global data I/O line 904, the potential on global data I/O line 904 returns from the ground voltage level to the power supply voltage level after completion of writing. This rising of potential on global data I/O line 904 is conducted to ground line 906 through parasitic capacitance 910, so that the potential on ground line 906 rises. Ground line 906 is electrically connected to nonselected sub-word line SWL. In accordance with potential rising caused by capacitive coupling of ground line 906, the potential on nonselected word line SWL rises, so that access transistor MT starts to be turned on, and electric charges accumulated in capacitor MQ flows onto bit line BL.
Particularly, semiconductor memory devices in these days employ a low power supply voltage of 2.0 V or lower and access transistor MT has a small threshold voltage. Therefore, in accordance with the rise of potential on nonselected sub-word line SWL, access transistor MT is turned on, and a relatively large leak current I1 flows from capacitor MQ to bit line BL. Leak current I1 flows every time data writing is performed in a fast serial access mode such as a page mode. As shown in FIG. 17, therefore, charges accumulated in memory capacitor MQ are gradually discharged, and the stored information is lost. This results in "disturb refresh failure", i.e., a problem that charges accumulated in memory capacitor MQ are discharged within a period shorter than the predetermined refresh cycle, and therefore the stored information in memory cell MC is lost. Since the global data I/O bus line and the ground line are provided commonly to the respective memory blocks in the column block, the parasitic capacitance 910 has a large capacitance value, and floating up of potential on the nonselected sub-word line occurs to a higher extent.
Global data I/O bus lines 902 and 904 are arranged adjacent to ground line 906, because it is necessary to arrange sub-decode lines 900 and 908 in accordance with the transistor pitch of the sub-decoder. Since the sub-decoder drives the sub-word line and has a relatively large current driving capability, the transistors thereof have a relatively large size. Therefore, the above arrangement is employed for sufficiently increasing an allowable size in the row direction for the sub-decoder.
Therefore, it is difficult to reduce the capacitive coupling between the ground line and the global data I/O line in the conventional layout of the sub-decoders.